The present invention relates to methods, systems and computer programs for producing integrated circuits (IC) that contain non-linear devices, and more specifically for producing ICs by simulating the performance of an IC that includes a time-dependent-impedance component.
Simultaneous switching noise (SSN) is defined as a noise voltage induced onto a single victim Input/Output (I/O) pin of an electronic component due to the switching behavior of other aggressor I/O pins in the device. This noise is considered in the context of either an output I/O driver victim or an input I/O buffer victim. Noise injected onto the pin of an output buffer will be attenuated by the effects on the connected transmission line, termination network, and receiver load. The shape of this noise pulse at the receiver, the far-end, is critical when considering SSN effects on output buffers. This far-end pulse can cause timing and voltage level errors.
Using linear superposition methods in performance simulations allows the SSN on a victim pin to be calculated through the superposition of many short simulations, each composed of a single aggressor pin switching. In some cases, linear superposition simulation techniques can be applied to non-linear systems and still yield good accuracy while improving the simulation time required. An example of this is the QUARTUS™ SSN Analyzer that uses superposition to model SSN caused by non-linear I/O buffers. While this model is quite accurate for many I/O configurations, the accuracy of the model decreases for slow slew rate standards due to the increased non-linearity of a slow switching I/O buffer.
It is in this context that embodiments of the invention arise.